1. Field of the Invention
This invention relates to a memory array, and more particularly, a one-time programmable memory array having small chip area.
2. Description of the Prior Art
Non-volatile memory (NVM) is a type of memory that retains information it stores even when no power is supplied to memory blocks thereof. Some examples include magnetic devices, optical discs, flash memory, and other semiconductor-based memory topologies. According to the programming times limit, non-volatile memory devices are divided into multi-time programmable (MTP) memory and one-time programmable (OTP) memory.
FIG. 1 shows a conventional OTP memory array 10 of prior art. The memory array 10 includes a plurality of memory cells 100, each including a select transistor 110, a following gate transistor 120 and an antifuse transistor 130. The select transistor 110 is used to select the memory cell to be programmed. To avoid the select transistor 110 from being broken down due to the high voltage when programming the memory cell 100, the following gate transistor 120 is added between the antifuse transistor 130 and the select transistor 110. When programming the memory cell 100, the antifuse transistor 130 is ruptured and behaves as a metal-oxide-semiconductor capacitor, such that data of logic “1” can be written into the OTP memory cell 100.
FIG. 2 shows a layout of the OTP memory cells 100. In FIG. 2, the two memory cells 100 are disposed in two different active areas AA1 and AA2 respectively. Also, due to the design rule of the layout, isolation structures, such as dummy poly PO and poly over diffusion edge PODE, are added between the active areas for the stability of the manufacturing process. Similarly, all the OTP memory cells 100 of the OTP memory array 10 are disposed in different active areas. Therefore, the dummy isolation structures can be found everywhere in the layout of the OTP memory array, which largely increases the chip area required by the OTP memory array 10. Thus, how to use the chip area more efficiently and design a memory array with small chip area has become an issue to be solved.